A conventionally known example of electrically rewritable nonvolatile memory is flash memory which is configured as a cell array of NAND-connected or NOR-connected memory cells each having a floating gate structure. Also known as a nonvolatile memory capable of high speed random access is ferroelectric memory.
In addition, a technology proposed to achieve increased miniaturization of memory cells is resistive type memory which uses a variable resistor as the memory cell. Known examples of the variable resistor include the likes of a phase change memory element in which the resistance value is varied by changing between the crystalline and amorphous states of a chalcogenide compound, an MRAM element which utilizes resistance variation due to tunnel magnetoresistance effect, a polymer ferroelectric RAM (PFRAM) element which has a resistor formed by a conductive polymer, and a ReRAM element in which resistance variation is caused by electrical pulse application.
Of these, the variable resistor used in ReRAM is broadly divided into ones in which resistance variation occurs due to presence/absence of a trapped charge in a charge trap existing at an electrode interface and ones in which resistance variation occurs due to presence/absence of a conductive path induced by oxygen deficiency or the like.
Moreover, the variable resistor used in ReRAM has two kinds of operation modes. In one, referred to as bipolar type, the polarity of applied voltage is switched to set a high-resistance state and a low-resistance state. In the other, referred to as unipolar type, the voltage value and voltage application time are controlled, thus allowing the high-resistance state and the low-resistance state to be set without switching the polarity of applied voltage.
In conventional technology, when performing a rewrite operation of the memory cell, a rewrite voltage is applied for a constant time on a number of occasions and, on each occasion, a verify operation is performed to confirm success/failure of the rewrite. However, the fact that there is variation in the rewrite time of memory cells and that a pass is not achieved in verify until the rewrite operation is completed for all the memory cells leads to the problem that, even though rewrite is completed for the majority of memory cells, rewrite time is determined by a portion of memory cells having slow rewrite speed. In conventional technology, the rewrite condition of such memory cells cannot be ascertained from the outside, and it is thus difficult to shorten the cycle time.